Field of the Invention
The present invention relates to image processors, and more particularly, to an image processor that derives a CABAC_ZERO_WORD to be included in Network Abstraction Layer (NAL) unit packets in generating NAL unit packets of the H.264 compression coding format.
Description of the Background Art
The H.264 compression coding format, one of compression coding formats for moving images, requires as an H.264 standard to derive a parameter called CABAC_ZERO_WORD to insert into a stream in employing Context-Adaptive Binary Arithmetic Coding (CABAC) as a coding format.
JP2009-071598A describes various examples of ⅓ multipliers configured with multiple bit shift circuits and multiple adders.
Derivation of a CABAC_ZERO_WORD is normally performed with a software program written in, for example, the C language. Since the C language allows for floating-point arithmetic, employing the C language realizes operations in conformity with an algorithm for calculating CABAC_ZERO_WORD as required by the H.264 standard.
In methods where the CABAC_ZERO_WORD is calculated with a software program, however, calculation of the CABAC_ZERO_WORD occupies processing power of a CPU, causing an elongated time required to generate NAL unit packets for a CPU having a low processing speed. Thus use of methods where the CABAC_ZERO_WORD is calculated with a software program is limited in light of increasing frame rates and compatibility with networks of moving images accompanied by increasing loads for a CPU.